In the fabrication process of classical CMOS devices, topography has always been reduced as much as possible in order to facilitate the patterning of the different levels, affecting the quality of both lithography and dry etching steps. The development of Shallow Trench Isolation or STI (used for active area pitches in the sub-0.5 μm regime) and, more specifically, the reduction of the ‘STI ditch’ at the border between active area and field is a typical example in this context. Gate patterning is another example of such a critical application.
In general, topography consists of two facets: the level difference on local scale and the slope of the surface caused by this level difference. The former compromises the lithographic illumination conditions because sufficient Depth of Focus (DOF) is required. From (anisotropic) dry etch point of view, both level difference and slope determine the final process window. In the neighborhood of a topography step a deposited, grown, or spin-coated layer is locally thicker in the direction perpendicular to the wafer compared to this layer on a flat surface. The steeper the slope and the larger the level difference, the longer over-etch is needed to clear out the residual parts of the layer next to the topography steps. Referring back to the example of the STI ditch, during gate etch, a sufficiently long over-etch is needed to remove poly-Si residues, which requires high selectivity towards the gate oxide and adequate profile control (e.g., to prevent notching).
In many cases topography reduction is not straightforward. In Non-Volatile Memory (NVM) applications, the control gate level is patterned as a three-dimensional structure on top of the floating gate. A reduced topography can be achieved by patterning the floating gate with a sloped profile (typically between 80 and 85 degrees). However, the height of the floating gate is fixed by the technology node (e.g., 125 nm for 0.13 μm technology), and the overall topography remains very pronounced.
In some cases topography is a crucial part of the device architecture, e.g., for Multi-Gate devices which are regarded as possible alternatives for classical CMOS devices in sub 45-nm technologies. The term “Multi-Gate device” or “MuGFET” refers to a family of devices known in literature as FinFETs, Tri-gate, Omega-gate, Pie-gate, and the like. The potential advantage of these devices is their superior short-channel effect (SCE) control over bulk devices in the sub-30 nm physical gate length regime. Important issues in the fabrication of these devices are, e.g., the patterning of 25 nm gates over high topography due to the fins. In MuGFETs the active area is patterned from an SOI (Silicon On Insulator) layer of the order of tens of nm thick, and consists of source and drain connected by ‘fins’. Narrow fins are required to have a better short channel effect control. Typically the fin width should be about half of the gate length. The channel width on the other hand is determined by the height of the fin—the higher the fin, the more current can flow from source to drain. Therefore the gate stack is deposited on a surface with an intrinsically high topography.
One of the key issues of gate patterning for MuGFETs is the high topography involved. The FIN heights are of the order of 50 to 100 nm, and recess in the BOX (Buried Oxide Layer) can result in extra topography, from a few nm to several tens of nanometers. As a consequence, the selectivity of the etch chemistries used for gate patterning become more critical than compared to planar gate etch. For each layer that needs to be etched, a sufficiently long over-etch is required to clean up any residues at topography steps while at the same time damage to already patterned layers must be avoided.
The patterning of the gate for MuGFETs consists of four basic steps. First several layers are deposited (or grown/coated) on the initial surface: the layer(s) that need(s) to be patterned (e.g. poly-Si or a stack of metals to define the gate); sacrificial layers (e.g. stopping layer, hard mask); and litho-related layers (e.g. Bottom Anti Reflective Coating or BARC, resist). Second, the wafer is illuminated and the resist developed. Subsequently the wafer is etched to transfer the resist pattern into the relevant layer(s) stopping on the initial surface. In the fourth and last step, any sacrificial material (e.g. resist, hard mask) is removed. As mentioned before, the presence of topography steps narrows down the process window for both lithography and dry etch. Since the topography itself in many cases can only be reduced to some extent, other options have to be explored to open up the process window as much as possible.
One approach that has been used to avoid problems related to the etching of layers with high topography is Chemical Mechanical Polishing (CMP) to planarize the surface of one of the layers that is deposited on the initial surface. This is certainly a huge improvement from lithographic point of view with respect to DOF. From dry etch point of view this approach has the advantage that any layer that is deposited on top of this planarized layer (e.g., hard mask on top of CMP-ed poly-Si used for gate patterning) can be removed with minimal over-etch. Yang et al. (Symp. on VLSI Technology 2004 pp. 196) have successfully applied this approach to pattern a poly-Si gate with a CD of 5 nm (using hard mask trimming) on top of a nanowire FinFET structure. The level difference between the top of the fin and the BOX is about 15 nm, whereas the poly thickness is about 60 nm. Nevertheless, there are two serious drawbacks of the CMP approach. First, the uniformity and reproducibility of the CMP process are difficult to control since there is no stopping layer. Second, as the etch front is planar, the higher-level parts of the initial surface will be exposed sooner to the etch plasma. In the case of MuGFET poly-Si gate patterning this means that source, drain and fin become exposed to the plasma when there is still a relatively thick poly-Si layer present on field areas. On the one hand this complicates the use of endpoint triggering (typically used for planar gate etch) and on the other hand it is problematic for the removal of the remaining poly-Si—etch chemistries with very high selectivity to gate oxide tend to have poor profile control and a very small etch rate (especially when considerable amount of poly-Si is exposed to the plasma).
U.S. Pat. No. 6,787,476 by Dakshina-Murthy et al. describes the use of a stopping layer in between two layers where the removal of the upper layer causes selectivity problems with respect to the lower layer (due to the long over-etch needed because of topography). This approach was used for MuGFET gate etch, and more specifically for an ARC (Anti-Reflective Coating) layer (e.g., SiN) on poly-Si. The stopping layer consists of Ti or TiN because these materials have a very low etch rate in a fluorine etching process, such as, for example, a CF4/Ar etching process for which the ARC layer and poly-Si have a high etch rate. Subsequent to etching of the ARC, the etch stop layer and poly-silicon material of the gate may be etched using, for example, a Cl2/HBr etching process. This approach has the overall disadvantage that an additional layer is added to the stack—after gate etch it needs to be removed with sufficient selectivity towards materials like poly-Si and oxide, which complicates the process flow. Another disadvantage is the fact that the etch chamber becomes metal contaminated. During front-end-of-line CMOS processing metal contamination is avoided when possible. The metallic stopping layer used here is not a part of the gate itself but only used for patterning purposes. If an alternative without metal contamination is possible, then this is more preferable.
Dakshina-Murthy et al. propose an additional approach to tackle the problem of topography for MuGFET gate etch. First, the gate oxide and the poly-Si layer are deposited on the initial surface with active area. On top, an endpoint layer (e.g., Ti or SiGe) is deposited followed by an additional poly-Si layer or possibly another material (not specified). First the additional layer is etched on endpoint, stopping on the Ti or SiGe layer, resulting in spacers next to topography steps. These spacers reduce the slope of the topography and therefore less ARC OE is needed. From this point onwards, the rest of the patterning is continued (possibly with the use of a Ti or TiN stopping layer suggested before). Also, this second proposal by Dakshina-Murthy et al. has disadvantages because again extra layers are added to the stack and in addition, an etch on endpoint to create spacers next to the topography steps is needed. This complicates the process flow even more than in the case of their first proposal. The gate etch itself becomes more complicated with respect to selectivity towards the spacer material. Finally, if Ti is used as a stopping layer, then the etch platform becomes metal contaminated.